Memory devices are used for internal or external storage in electronic components including, but not limited to, computers, digital cameras, cell phones, MP3 players, personal digital assistants (PDAs), video game consoles, and other devices. There are several different types of memory devices, including volatile and non-volatile memory. Volatile memory devices require a steady flow of electricity to maintain their contents, such as for example, random access memory (RAM). Non-volatile memory devices retain or store information even when electrical power to the electronic component is terminated. For example, read-only memory (ROM) can hold instructions for operating an electronic device. EEPROM (electrically erasable programmable read-only memory) is a type of non-volatile read-only memory (ROM) that can be erased by exposing it to an electrical charge. EEPROM typically comprise a number of memory cells that each have an electrically isolated floating gate to store charge which is transported to, or removed from, the floating gate by programming or erase operations.
One type of EEPROM is a memory cell that has a floating gate field-effect transistor capable of holding a charge, such as a flash memory cell. The flash memory cell provides both the speed of volatile memory, such as RAM, and the data retention qualities of non-volatile ROM. Advantageously, an array of memory cells can also be electrically erased or reprogrammed using a single electrical current pulse instead of one cell at a time. A typical memory array includes a large number of memory cells grouped into an erasable block. Each of the memory cells can be electrically programmed basis by charging the floating gate and the stored charge can be removed from the floating gate by an erase operation. Thus, the data in a memory cell is determined by the presence or absence of the charge in the floating gate.
An exemplary memory cell 20 comprises a substrate 22 comprising a source 24 and a drain 26, and channel 28 therebetween, as shown in FIG. 1. A tunnel oxide layer 30 allows electrons traveling between the source 24 and drain 26 to move to a floating gate 32 which holds charge. An inter-gate dielectric 34 lies above the floating gate 32 and a control gate 36 is over the inter-gate dielectric 34. The substrate 22 typically comprises a p-doped silicon wafer, and a source 24 and drain 26 which are both n-doped regions. The floating gate 32 and control gate 36 are typically made from polysilicon, and the inter-gate dielectric 34 is made from a silicon oxide/silicon nitride/silicon oxide layer commonly referred to as an O/N/O gate.
Flash memory cells 20 with higher memory densities are being developed to increase data storage capacity and reduce manufacturing costs. The memory density and data storage capacity of a memory cell 20 can be increased by reducing the minimum feature size of the cell. As the sizes of the features of the memory cell are reduced to ever-smaller levels of less than 90 nm, the thickness “t” of the tunnel oxide layer 30 is also correspondingly reduced. The thinner tunnel oxide layer 30 allows lower operational voltages to be used to induce electron movement from the channel 28 through the tunnel oxide layer 30 and to the floating gate 32. The lower the operational voltages used to program the memory cell 20, the lower the energy consumption of the cell 20, which is desirable.
However, while a memory cell 20 having smaller features can provide increased data storage capacity and reduced energy consumption, the data retention time of the cell 20 often undesirably decreases as the tunnel oxide layer 30 becomes thinner. The data retention time is the time duration for which the programmed charge remains in the floating gate 32 of the cell 20 without dissipation. Typically, electrons in the floating gate 32 gradually tunnel back across the tunnel oxide layer 30 over a period of time. The leakage current of the cell 20 is a current that occurs from electrons traversing the tunnel oxide layer 30 during a storage cycle or idle period of a programmed cell 20. The leakage current eventually results in total discharge of the charge stored in the cell 20 resulting in the loss of the data or information stored in the cell 20. The higher leakage current and increased charge tunneling occurring in the thinner tunnel oxide layer 30 reduces the charge retention time in the floating gate. Reduction in thickness of the tunnel oxide layer 30 also degrades the quality of the tunnel oxide thereby further increasing the flow of leakage current. Also, the properties of the tunnel oxide layer 30 generally degrade over time as it is subjected to consecutive charging and erase cycles.
While higher memory density and reduced energy consumption are desirable, it is also desirable to increase the data retention time of the memory cell 20. For example, various methods of operating memory cells 20 have been developed to reduce the leakage current through the tunnel oxide layer 30 while still minimizing its thickness. For example, U.S. Pat. No. 6,580,640 to Kao, which is incorporated herein by reference in its entirety, discloses a method of operating a memory cell 20 in which a positive charge is placed on a control gate 36 of the cell 20 to improve data retention of the electrons placed on the floating gate 32 of the cell 20. The positive charge causes the electrons on the floating gate 32 to migrate away from the tunnel oxide layer 30 of the cell 20 thereby reducing leakage currents. While this is an acceptable method of operation, it requires additional electrical power to place the positive charge, thereby increasing the power consumption of the cell 20.
Thus it is desirable to increase the memory density and storage capacity of a memory cell while still providing acceptable data retention times. It is also desirable to minimize the size of the features of the cell without excessive leakage current. Memory cells that use less energy are also more desirable for power saving applications.